Design a Synchronous Circuit's Timing — Project Guide

🧑‍🔧 Design a Synchronous Circuit's Timing

Field: Digital Logic / Computer Engineering

Written and maintained by the PhDino author · Last reviewed 21 September 2026 · Every calculator used here is tested against independent reference values · how PhDino checks its numbers

Work out your critical path delay, pick a clock period that respects it, then confirm the flip-flops on that path actually meet setup and hold.

Getting a synchronous digital circuit's timing right comes down to three questions asked in order: how long does the slowest combinational path actually take to settle, what clock period does that imply, and, using that same clock period, do the flip-flops on that path actually meet their setup and hold requirements? Each answer feeds directly into the next.

This guide reuses the critical path delay in two different places, and the chosen clock period in a third, which is exactly the sequence a real synchronous design review runs through. It also shows why the last check is run twice: setup is decided by the slowest path and hold by the fastest.

🧮 Logic Gate Propagation Delay 🧮 Clock Frequency & Duty Cycle 🧮 Flip-Flop Setup/Hold Margin

What setup and hold actually protect

A flip-flop captures its input on a clock edge. For the capture to be reliable, the data must be stable for a short time before the edge, the setup time, and stay stable for a short time after it, the hold time. Break either and the flip-flop may settle to the wrong value, or hang for a while between the two, a state called metastability, which shows up as rare and unrepeatable failures.

The two checks have opposite enemies. Setup fails when a path is too slow for the clock, and the cures are a slower clock, faster logic, or fewer gates in the path. Hold fails when a path is too fast, so new data races through before the old data has been safely captured, and slowing the clock does not help at all, because the check never involves the clock period.

The three delays in every path

Between two flip-flops, a signal has to leave the first, cross the combinational logic and arrive at the second in time. That puts three delays in every setup check: the clock-to-Q delay of the launching flip-flop, the propagation delay through the logic, and the setup time of the capturing flip-flop. Their sum must fit inside one clock period.

A quick estimate that counts only the gates leaves out the other two, which is why the frequency implied by gate delay alone is an upper bound and never a design value.

Steps

1🚪Logic Gate Propagation Delay
Enter your critical path's gate delay and logic depth (the number of gates in the longest signal path). This returns the total propagation delay and the clock frequency it implies. That frequency is an upper bound only, because it leaves out the flip-flops' own delays. Hit "📋 Copy Values" once you have a result: the total delay carries into both of the next two steps.
🧮 Open the Logic Gate Propagation Delay calculator
2⏰Clock Frequency & Duty Cycle
"📥 Paste Values" fills in Clock Period with Step 1's total delay as a starting point. Replace it with a real period: at least the clock-to-Q delay plus the path delay plus the setup time, and then some margin for variation. Check the resulting frequency and the high and low times. Hit "📋 Copy Values" once you've settled on a period: it carries into the final step.
🧮 Open the Clock Frequency & Duty Cycle calculator
3🩴Flip-Flop Setup/Hold Margin
Paste twice here: first from Step 1 to fill in Combinational Delay, then from Step 2 to fill in Clock Period. Add your flip-flop's clock-to-Q, setup and hold specs (from its datasheet). The calculator uses one combinational delay for both margins, so run it twice: with the longest path to read the setup margin, and with the shortest path to read the hold margin. If either margin is negative, the design doesn't work yet.
🧮 Open the Flip-Flop Setup/Hold Margin calculator

Worked example: a 12-gate critical path at 4 ns

A pipeline stage has a critical path of 12 gates at 0.25 ns each. The flip-flops have a clock-to-Q delay of 0.4 ns, a setup time of 0.15 ns and a hold time of 0.10 ns. The shortest path between the same two flip-flops is a single gate.

Step 1: The critical path

You enter	Value
Delay per Gate	0.25 ns
Logic Depth (gates in critical path)	12

The calculator returns	Value
Total Propagation Delay	3.00 ns
Implied Max Clock Frequency	333.3 MHz

12 gates at 0.25 ns is 3.00 ns of propagation delay. If the clock period could equal that, the frequency would be 333 MHz, and that is the number the calculator reports.

Treat it as an upper bound. The clock period must also cover the launching flip-flop's clock-to-Q delay and the capturing flip-flop's setup time, so the true minimum is 0.4 + 3.00 + 0.15 = 3.55 ns, or 282 MHz. Counting only the gates would have overstated the achievable frequency by 18 percent.

Step 2: Choosing the clock period

You enter	Value
Clock Period	4 ns
Duty Cycle	50 %

The calculator returns	Value
Clock Frequency	250.000 MHz
High Time	2.000 ns
Low Time	2.000 ns

The handoff from step 1 would drop in the bare 3.00 ns as a starting period. We replace it with 4.0 ns, which is 13 percent above the 3.55 ns minimum: a margin against variation in process, voltage and temperature, and against the effects the simple check leaves out.

That is a clock of 250 MHz, high for 2.0 ns and low for 2.0 ns at a 50 percent duty cycle. For ordinary edge-triggered flip-flops only the period enters the checks below.

Step 3: Setup, with the longest path

You enter	Value
Clock Period	4 ns
Clock-to-Q Delay	0.4 ns
Combinational Logic Delay	3 ns
Flip-Flop Setup Time	0.15 ns
Flip-Flop Hold Time	0.1 ns

The calculator returns	Value
Setup Margin	0.45 ns
Hold Margin	3.300 ns

Setup is decided by the slowest path, so we enter the 3.00 ns critical path. The setup margin is the period minus everything that must fit inside it: 4.00 − (0.40 + 3.00 + 0.15) = 0.45 ns. It is positive, so the slowest path arrives with 0.45 ns to spare.

Ignore the hold margin printed in this run. The calculator uses one logic delay for both checks, and this run used the longest path, which is the wrong one for hold.

Step 4: Hold, with the shortest path

You enter	Value
Clock Period	4 ns
Clock-to-Q Delay	0.4 ns
Combinational Logic Delay	0.25 ns
Flip-Flop Setup Time	0.15 ns
Flip-Flop Hold Time	0.1 ns

The calculator returns	Value
Setup Margin	3.200 ns
Hold Margin	0.55 ns

Hold is decided by the fastest path, here a single gate of 0.25 ns. The hold margin is the clock-to-Q plus that delay minus the hold time: 0.40 + 0.25 − 0.10 = 0.55 ns. It is positive, and notice that the clock period appears nowhere in it, so slowing the clock could not have rescued it. Ignore the setup margin printed in this run.

The calculator has no skew input, but skew subtracts directly from the hold margin. If the capturing flip-flop's clock edge arrives 0.6 ns later than the launching one, the margin becomes 0.55 − 0.6 = -0.05 ns: a hold violation, cured by adding delay to that short path or by fixing the clock distribution, never by changing the frequency.

What it adds up to

The setup check passes with 0.45 ns on the slowest path, and the hold check passes with 0.55 ns on the fastest. The second is the one that deserves suspicion, because it does not depend on the clock and a modest skew erases it. A design that meets setup at the target frequency can still fail hold at any frequency.

Real designs are checked by static timing analysis tools, which do this for every path, in every process and temperature corner, with skew and jitter included. A hand check like this one is for boards and small designs, and for understanding what those tools report.

Notes & limitations

Both pastes into the final step are separate actions (paste from Step 1, then separately paste from Step 2). Each only fills in its own mapped field, so doing them in either order is fine as long as both happen before reading the result.
A rigorous analysis also accounts for clock skew and for variation in process, voltage and temperature, neither of which this simplified sequence includes (see the Flip-Flop Setup/Hold Margin article). Skew is why the hold check in the worked example is the one that deserves suspicion.

Mistakes in hand timing checks

These are the slips that make a design pass on paper and fail on the bench.

Using the same logic delay for setup and hold. Setup needs the longest path and hold the shortest, and the calculator's single input means running it twice.
Forgetting clock-to-Q and setup, and taking the frequency from gate delay alone. In the example that overstates the achievable speed by 18 percent.
Trying to fix a hold violation by slowing the clock. It cannot work, because hold does not depend on the period.
Checking only typical delays. Datasheets give minimum and maximum values, and setup should be checked at the maximum, hold at the minimum.
Ignoring skew and jitter. Both subtract from the margins, and skew in particular can flip a healthy hold margin negative.
Sampling an asynchronous input directly. A signal from another clock domain or a button needs a synchronizer, typically two flip-flops in series, because no setup and hold check can be met for a signal that changes at any time.

When a hand check is not enough

Once a design has many paths, several clocks or a fast clock, use the timing analysis that your FPGA or chip tool provides. It sums the real delays, including wiring, for every path and reports the worst, which no hand check can match.

Still, the calculators here are the same arithmetic in miniature, and reading a timing report is much easier when you have done these three checks by hand once.

Frequently asked questions

What is metastability?

It is what happens when a flip-flop's input changes too close to the clock edge for it to decide cleanly. The output can hover between the two logic levels for an unpredictable time before settling, and it may settle to either value. It cannot be prevented for asynchronous inputs, only made very rare by using synchronizers.

Why does the hold margin not depend on the clock period?

Because hold compares two things that happen around the same clock edge: how soon new data can arrive after that edge, and how long the flip-flop needs the old data to stay. The next edge, one period later, is not involved.

How much timing margin should I leave?

Enough to cover variation in process, voltage and temperature and the effects the simple check omits, and the right amount depends on the technology and the design. The example uses 13 percent above the minimum period, which is a plausible illustration and not a rule.

How can I fix a setup violation without slowing the clock?

Shorten the path: use faster gates, reduce the logic depth, or split the logic across two stages by adding a pipeline register. Each option costs something in area, power or latency, which is why a slower clock is sometimes the pragmatic answer.

What does the duty cycle change?

It sets how long the clock stays high and low. For plain edge-triggered flip-flops only the period matters to setup and hold, but the high and low times must still meet each device's minimum pulse width, and they matter a great deal for latches and for circuits that use both clock edges.