🚪 Logic Gate Propagation Delay

Written and maintained by the PhDino author · Last reviewed 21 September 2026 · Checked against 1 independent reference calculation · how PhDino checks its numbers

Why a chain of logic gates takes real time to settle, and what that means for how fast a circuit can run.

A logic gate doesn't change its output the instant its input changes — there's a small but real propagation delay while the underlying transistors switch and the output settles to its new value. In a combinational circuit built from several gates in series (the "critical path" — the longest chain of gates a signal has to pass through), those individual gate delays add up to a total propagation delay for the whole path.

That total delay directly caps how fast a synchronous circuit built from this logic can be clocked: the clock period has to be at least as long as the slowest (critical) path's propagation delay, or a downstream flip-flop will try to capture a signal that hasn't finished settling yet — which is exactly what setup time margin (covered elsewhere) checks for.

Key formula

Total propagation delay = gate delay × logic depth
Implied max clock frequency ≈ 1 ÷ total propagation delay

Variables

logic depth

the number of gates in the longest (critical) signal path through the combinational logic

Notes & limitations

• This assumes every gate in the path has the same delay, which is a simplification — real gates have different delays depending on their type, fan-out (how many other gates they drive), and the specific transistor technology, so a real critical-path analysis uses each gate's actual datasheet or simulated delay rather than one uniform number.
• Total propagation delay is one piece of the full timing picture — it feeds directly into a proper setup-time check (see Flip-Flop Setup/Hold Margin), which also accounts for clock-to-Q delay and the flip-flop's own setup time requirement.