⏰ Clock Frequency and Duty Cycle

Written and maintained by the PhDino author · Last reviewed 21 September 2026 · Checked against 2 independent reference calculations · how PhDino checks its numbers

The relationship between a clock signal's period, its frequency, and how long it spends high versus low each cycle.

A digital clock signal is a repeating square wave, and its frequency (how many cycles happen per second) is simply the inverse of its period (how long one full cycle takes) — the two describe exactly the same signal from two different, equally valid angles, whichever is more convenient for a given calculation.

Duty cycle describes the shape of that square wave within each period: the fraction of the period the signal spends "high" versus "low." A 50% duty cycle (equal high and low time) is extremely common for general clock distribution, but other duty cycles show up deliberately in applications like PWM (pulse-width modulation) motor control, where the duty cycle itself — not just the frequency — is the value being controlled.

Key formula

Frequency = 1 ÷ period
High time = period × duty cycle
Low time = period − high time

Notes & limitations

• Real clock signals aren't perfect square waves — actual rise/fall times, jitter (cycle-to-cycle timing variation), and duty-cycle distortion all exist in real hardware, though they're usually small enough to ignore for basic frequency/period planning.
• A circuit's clock period has to be long enough to satisfy the slowest signal path's propagation delay plus setup time — see Logic Gate Propagation Delay and Flip-Flop Setup/Hold Margin for how a clock period gets checked against real circuit timing, not just chosen freely.