🩴 Flip-Flop Setup and Hold Timing

Written and maintained by the PhDino author · Last reviewed 21 September 2026 · Checked against 1 independent reference calculation · how PhDino checks its numbers

The two timing checks that determine whether a synchronous digital circuit will actually work at a given clock speed.

A flip-flop only reliably captures the data at its input if that data has been stable for a minimum time before the clock edge (setup time) and remains stable for a minimum time after the clock edge (hold time). If either requirement is violated, the flip-flop can enter an unpredictable, unstable state (metastability) instead of cleanly capturing a 0 or a 1 — a real failure mode in synchronous digital design, not just a theoretical concern.

Setup checking asks whether data arrives early enough: starting from one clock edge, data has to travel through a launching flip-flop's own clock-to-Q delay, then through any combinational logic between the two flip-flops, and still arrive with enough time left before the next clock edge to satisfy the receiving flip-flop's setup requirement. Hold checking is different in character: it asks whether data changes too soon after the clock edge that just captured the previous value, which is why hold checks depend on the fastest (not slowest) path delay and don't involve the clock period at all.

Key formula

Setup margin = clock period − (clock-to-Q delay + combinational delay + setup time)
Hold margin = (clock-to-Q delay + combinational delay) − hold time

Variables

clock-to-Q

delay from a clock edge to the launching flip-flop's output actually changing

Notes & limitations

• Both margins need to be positive for the design to work reliably — a negative setup margin means the clock is running faster than the logic can keep up with; a negative hold margin means data is changing too soon, which no amount of slowing the clock down can fix (hold violations are a same-cycle problem, independent of clock speed).
• This is a simplified single-number model — a rigorous timing analysis uses separate maximum-delay and minimum-delay values for the combinational path (since the true worst case for setup and the true worst case for hold generally come from different physical paths) and also accounts for clock skew (the clock arriving at the two flip-flops at slightly different times), neither of which this simplified version includes.